TSMC's first 1nm A10 process is proposed, with plans to achieve single chip packaging of 1 trillion transistors by 2030

At the IEDM conference, TSMC formulated a chip packaging route that includes 1 trillion transistors, similar to the plan disclosed by Intel last year.

Of course, 1 trillion transistors are a collection of 3D packaged small chips from a single chip package, but TSMC is also committed to developing 200 billion transistors for a single chip.

To achieve this goal, the company reiterates its commitment to 2nm level N2 and N2P production nodes, as well as 1.4nm level A14 and 1nm level A10 manufacturing processes, which are expected to be completed by 2030.

TSMC's first 1nm A10 process is proposed, with plans to achieve single chip packaging of 1 trillion transistors by 2030

▲ TSMC PPT obtained from Tom's Hardware

In addition, TSMC expects its packaging technology (CoWoS, InFO, SoIC, etc.) to continuously improve, enabling it to build large-scale multi chip solutions that package over 1 trillion transistors around 2030.

TSMC also revealed at the meeting that its 1.4nm level process development has been fully launched. Meanwhile, TSMC reiterated that the 2nm process will begin mass production as planned in 2025.